Create SystemVerilog (SV) design source descriptions for the various component parts of a Bit Error Rate Tester system for use in the testing of a digital communication system.

Digital Design Automation – EN0720 (KD7020) Assignment 2017-18

Design and Verification of an FPGA-based Bit Error Rate Tester


• To create SystemVerilog (SV) design source descriptions for the various component parts of a Bit Error Rate Tester system for use in the testing of a digital communication system.

• To perform simulations of individual design modules using SV test-modules and the Vivado® Simulator.

• To perform simulations of the complete BERT design top-level module using a SV test- module and the Vivado® Simulator.

• Synthesise and Implement the BERT system, targeting a Field Programmable Gate Array development board (Artix-7 FPGA on Digilent Basys3 development board).

• To perform post-implementation timing simulations of an individual module in order to verify correct operation after implementation.

• Demonstrate the operation of the FPGA implementation of the BERT using the development board by means of a so-called ‘loop-back’ test, and optionally, using a simple visible light communication link.

Learning Outcomes: See Assignment Specification document: ‘EN0720_KD7020_assignment_2017_18_Specification.docx’. Software and Hardware Resources:

• Xilinx Vivado ® FPGA/CPLD Design Suite. Available in labs E204/206 and as a free download (Vivado HLS WebPACK Edition) from: tools/vivado/vivado-webpack.html

• Digilent Incorporated ‘Basys3’ Artix-7 FPGA Development Board. Reference Manual.

Supporting Documentation (available on eLearning portal)

• Powerpoint presentation on Register Transfer Level Design using the SystemVerilog hardware description language.

Total number of marks available: 310

Description of the BERT System Figure 1a, below, shows a top-level block diagram of the Bit Error Rate Tester System and figure 1b shows the corresponding physical layout of the Basys3 development board. The system outputs a continuous stream of Manchester Encoded data bits on the ‘man_tx’ output pin, this signal is transmitted via the Visible Light Communication channel shown on the diagram. The received signal from the VLC is fed into the ‘man_rx’ input of the receiver part of the system, where it is decoded to produce the original transmitted data bits (RNRZ). By a process of synchronisation and comparison, the BERT system determines the number of bits that are received without error, for consecutive bursts of 1000 data bits, and displays this information on the 4-digit, 7-segment display. Synchronisation between the transmitted and received Non-Return-to-Zero (NRZ) data bits is achieved by manually adjusting the delay applied to the transmitted NRZ data bits, via the ‘Delay’ input switches, until a LED (SyncLED) indicates that synchronisation is achieved. The system is driven by a 100MHz crystal clock and an active-high reset push button, when pressed, resets the entire system. The highest data bit-rate of the system is one tenth of the master clock frequency, i.e. 10MBits/second. It may be necessary to reduce this data rate in order to perform a test with a simple VLC link having a lower bandwidth. This assignment involves the design, verification and implementation of the BERT system using a Field Programmable Gate Array (FPGA) device, this is achieved through a series of guided tasks. In addition, the characteristics of the VLC channel will be modelled and investigated by means of mixed-signal simulation.

Manchester  Data   Transmitterclock

rst Manchester  Data   Reciever





Delay Compare NRZD

Visible  Light   Communication


NRZ*  Data  Stream

Recovered  NRZ  Data  Stream

Delayed  NRZ Match  Count  (BCD)



Error  Control

NRZ*  -­‐  Non-­‐Return  to  Zero Bit-­‐Error-­‐Rate  (%)  =  (1000  –  Nc)/10

The  display  shows  the  number   of  correctly  received  data  bits   (Nc)  in  consecutive  bursts  of   1000  bits.


Figure 1a – Top-level block diagram of BERT system

The physical layout of the BERT system implemented using the Digilent® ‘Basys3’ development board, shown in figure 1b, illustrates the location of the main inputs and outputs. Eight sliding switches (SW0…SW7) are used to set the delay value when synchronising the transmitted and received data bits, while switches SW12 to SW15 are used to control error insertion.

A wire link is shown connecting ‘man_tx’ to ‘man_rx’ at the top right hand 10-way connector JB1, this constitutes the so-called ‘loop-back’ configuration.

E rr

or _o


E rr

R at


E rr

R at


E rr

R at




Delay Switches

man_tx (JB1)

man_rx (JB4)

Figure 1b – Physical layout of BERT system

Figure 1c, below, shows the internal block diagram of the Bit Error Rate Tester System.









Sync_control Pcount[9:0]















Display  Driver



Figure 1c – Internal block diagram of the BERT System

The system is made up of four main blocks, the majority of which are clocked by the system clock input (‘clock’) and asynchronously reset by means of the ‘rst’ input push-button. A Display Driver logic circuit outputs the ‘Match Count’ value to the multiplexed 4-digit, 7-segment display. All of the blocks in Figure 1c are SystemVerilog modules and, with the exception of the ‘Sync_control’ block, contain instances of sub-modules. Wherever possible, the names of ports and interconnecting signals should be kept the same in order to exploit the automatic port connection feature of the SV language. The system provides additional outputs ‘nrz’ and ‘man_bit_clk’ for testing purposes only, the Manchester encoded data bits being transmitted are on output ‘man_tx’. The Manchester Transmitter block contains a sub-module that allows errors to be inserted into the transmitted data stream corresponding to a range of bit-error rates from 1% to 50%, this allows the BERT system to perform self-testing when performing a so-called ‘loop-back’ test, i.e. ‘man_tx’ linked directly to ‘man_rx’. Task 1 – Create a SV source descriptions for the ‘ManchTrans’ block The timing diagram of figure 2a below shows the behaviour of the signals associated with the Manchester Encoding block (assuming the error insertion logic is disabled). The NRZ data stream is to be a Pseudo-Random Bit Sequence (PRBS) containing (2N – 1) bits, where ‘N’ is a parameter that sets the length of the PRBS shift register (set to 10 for implementation). The sequence continually repeats without interruption (apart from when the global system reset (rst) is asserted). The 100MHz main system clock is to be divided internally by 10 to result in a data bit rate of 10MBits/second. This achieved by means of an internal signal, ‘bit_en’ (bit enable), that pulses high for one clock period every 10, as shown by the red waveform in figure 2a.

Figure 2a – Timing Waveforms for Manchester Encoding Figure 2b shows the internal block diagram of the ‘ManchTrans’ block.

divclk prbsgen







ErrRate[2:0] Error_on



tbe D Q

clock rst







Figure 2b – Internal structure of the ‘ManchTrans’ block

As shown in the above diagram, a sub-module named ‘divclk’ generates the three basic timing signals (‘bit_en’, ‘bit_clk’ and ‘tbe’ in figure 2a) from a 4-bit, divide-by-10 counter signal (‘count’). Given that the signal ‘count’ goes from 0 to 9 repetitively: ‘bit_en’ is logic-1 when count equals 9

‘bit_clk’ is logic-1 when count is in the range 0 to 4 inclusive ‘tbe’ is logic-1 when count equals 4

Create a SV module for the clock divider ‘divclk’ having the module header provided below.

module  divclk  #(parameter  DIVIDER  =  10,  N  =  4)        (          input  logic  clock,          input  logic  rst,      //asynchronous  reset          output  logic  bit_en,                output  logic  bit_clk,              output  logic  tbe                );

The parameters ‘DIVIDER’ and ‘N’ allow the division r

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